FPGAs speed iris recognition

JANUARY 12, 2009--Iris recognition (IR) is one of the most accurate biometric identification methods available, with custom algorithms deployed globally in a variety of systems ranging from personal computers to portable scanners. Such iris recognition systems must reliably match a new template with one previously enrolled. The newly encoded iris is then compared to a database using a fractional hamming distance (HD) calculation.

Ryan Rakvic and his colleagues at Southern Methodist University have implemented this HD calculation using VHDL on a modern FPGA, and compared performance against a state-of-the-art CPU. The CPU used for this experiment was an Intel Xeon X5355 workstation-class machine, while the FPGA was executed on a DE2 board from Altera, which includes a Cyclone-II EP2C35 chip.

Execution and acceleration times indicated 383 ns per match for the optimized Xeon version versus 20 ns per match for the FPGA. Thus, the principal result so far demonstrates that the HD calculation on a FPGA of modest size is approximately 19 times faster than a state-of-the-art CPU design. Given traditional scaling of FPGAs, the algorithm running on a Stratix IV FPGA clocked at 500 MHz would perform a match in 2 ns. For more information, go to: http://spie.org/x31559.xml