INTERFACE STANDARDS: Camera Link 2 awaiting market drivers

As the only truly deterministic point-to-point camera interface currently available, Camera Link has rightfully gained its place as one of the most important camera standards. Originally developed nearly a decade ago, the standard allows a maximum data throughput of approximately 850 Mbytes/s of data to be transferred directly to a PC frame grabber.

Since its introduction, however, many sensor vendors have publicly announced or privately developed sensors and cameras that can capture images at much higher data rates. Two years ago, for example, Cypress Semiconductor (San Jose, CA, USA; www.cypress.com) announced its 3.0-Mpixel LUPA-3000 CMOS sensor, which provides a frame rate of 485 frames/s and a data throughput of 13.2 Gbits/s, developed for holographic data retrieval applications (see “Imagers speed holographic-data retrieval,” Vision Systems Design, March 2007). At VISION 2009 in Stuttgart, Germany, Awaiba (Madeira, Portugal; www.awaiba.com) showed a 16k × 1 linescan imager and prototype camera demonstration that required two Camera Link Full data interfaces running in parallel to support the camera’s data rate of 1.6 Gbytes/s.

“Unfortunately,” says Reynold Dodson, president of BitFlow (Woburn, MA, USA; www.bitflow.com), “the full data rate of these and other custom-developed imagers and cameras cannot be supported by the current Camera Link interface. Indeed, some of our customers are using high-speed image sensors that are throttled back to accommodate the current Camera Link standard in the hope that the next version of the standard will support faster data rates.”

Several companies including BitFlow are proposing a faster Camera Link standard. In BitFlow’s proposal, a number of serializer/deserializers (SerDes) are embedded in the same FPGA that controls the camera timing and control. Data is then transferred at 40 Gbits/s over a fiber connector.

It is a situation of which the Automated Imaging Association (AIA; Ann Arbor, MI, USA; www.machinevisiononline.org), the originator of the Camera Link standard, is fully aware. As yet, however, little progress has been made in developing a faster, more flexible successor. “One of the main reasons for this,” says Steve Kinney, chairman of the AIA Camera Link committee and director of technical pre-sales and support with JAI (San Jose, CA, USA; www.jai.com), “is the lack of a current market demand for such a standard. Indeed, more than 99% of current Camera Link cameras do not require anything faster than an 850-Mbyte/s data rate.”

Despite this, proponents of upgrading the original Camera Link standard are already proposing possible methods of implementation. “Such a standard,” says Dodson, “should not only support faster data rates. At present, the current Camera Link cables can only extend about 10 m, and in many cases, customers are forced into using fiberoptic extenders to increase this distance. As well, currently available 8-tap and 10-tap cameras are limited to 10-bit and 8-bit pixels, respectively.”

In high-speed scientific applications especially, bit depths of 12, 14, and 16 bits are required, which are not supported by the Camera Link standard. “However,” points out Kinney, “should a camera manufacturer wish to support such bit depths, it would be fairly easy to support these formats in the current Camera Link standard. Once again, there has been no such current market demand.”

“Luckily,” says Dodson, “the technology required to develop a successor to Camera Link—provisionally called Camera Link 2—is already available.” However, this will require a commitment from a number of camera and frame grabber companies.

In a presentation to the Camera Link committee at VISION 2009 in Stuttgart, Germany, Dodson presented his thoughts on how such an interface could be realized. The goal of Dodson’s proposal is a peer-to-peer standard that supports data rates of at least four times that of the current Camera Link standard, minimum 100-m cable lengths with fiberoptic support, and real-time camera control and bidirectional communication from the host PC to the camera. “Most important,” says Dodson, “the cost of development should be acceptable to small companies and there should be no ongoing license fees for IP support.”

To develop this standard, a number of serializer/deserializers (SerDes) could be embedded in the same FPGA that controls the camera timing and control (see figure). A 40-Gbit/s link requires four 10-Gbit/s serializers and four 10-Gbit/s deserializers, so FPGAs such as Altera’s Stratix IV GT could be used. Because this device features four independent 3.125-Gbit/s full-duplex channels per block, with up to 20 channels (in 5 blocks) per device, a 40-Gbit/s link could easily be accomplished.

Optical connectors such as Quadwire from Finisar (Sunnyvale, CA, USA; www.finisar.com) could then be used to transfer the data at 40 Gbits/s over a multimode fiber (MMF) ribbon cable. A high-speed interface like this would allow a number of pre-existing serial protocols such as InfiniBand or Serial RapidIO to be used.

Alternatively, the Camera Link committee could define its own protocol around the hardware. Whatever method is chosen, a new protocol would necessitate some work on behalf of the AIA since different pixel tap formats and pixel depths would need to be defined as well as the size and type of image, control, and communications packets transmitted.

“At present it seems,” says Dodson, “no one is willing to step up to the plate and pursue the Camera Link 2 specification, resulting in what amounts to a Catch 22 situation.” As Kinney points out, however, it may require more than a 1% market demand for such an interface to become reality. Perhaps, eventually, it will be the camera companies that are forced into developing a standard to support their latest devices. Until then, Camera Link 2 remains at least two years from becoming a reality.