'Stellar' simplification of FPGA design
Engineers at4DSP (Austin, TX, USA) are aiming to help design engineers -- including those developing image processing systems -- to simplify FPGA design.
Knowledge of anHDL language is not required to create new FPGA designs when using the company's new "Stellar IP" tool because it is designed to automate the creation of an FPGA by allowing designers to reuse proven IP cores to expedite embedded system design.
Designing using FPGAs has often been slated in the past as being a time-consuming process. Relying on existing IP to speed up this process has become essential and ensures that the FPGA portion of a system does not become a bottleneck in a tight design schedule.
4DSP does not claim that the new tool will solve all the problems inherent in designing an FPGA, but it does guarantee that it will help engineers complete their project faster by removing tedious steps out of the cycle.
"Programming software for a Stellar IP-based design is as simple as using a microcontroller. Designing a StellarIP FPGA firmware is even easier since it's only about interconnecting IP blocks to one another, either by using a text file or a graphical schematics editor. The tool takes care of the rest and prevents the user from having to deal with the intricacies of FPGA design," says Arnaud Maye, Embedded Systems Manager at 4DSP.
Stellar IP is available for free as part of the 4DSP Board Support Package targeting the 4DSP FMC and Virtex-6 FPGA product lines. It can be licensed for use with third party products.
A short video and technical information about Stellar IP can be found atwww.4dsp.com/stellarip.php.
-- By Dave Wilson, Senior Editor,Vision Systems Design