VLIW spells out computing for the next level
VLIW spells out computing for the next level
With the introduction of its Microprocessor Architecture for Java Computing (MAJC) architecture, Sun Microsystems (Palo Alto, CA) has thrown its hat into the ring of a number of companies now supporting very-long-instruction-word (VLIW) architectures. According to Sun, several microprocessor trends were identified and accommodated in the design of the MAJC architecture. These include the convergence of communication media and computers (audio, video, and data) and advancements in semiconductor technology that allow multiple processing units to be combined on a single chip.
The architecture, revealed at August`s HOT Chips 11 conference at Stanford University (Stanford, CA), suggests a basic implementation of a single processor unit with four functional units. By replicating those design elements, a CPU can be built that includes a few or even hundreds of processors, each with four functional units, each of which can operate on many data items simultaneously with parallel-operation instructions.
At the lowest level of parallelism, MAJC architecture provides single-instruction/multiple-data (SIMD) or "vector" instructions. A SIMD instruction executing in a single functional unit could perform the same operation on multiple data items simultaneously.
Of course, MAJC is not the first processor to encompass a VLIW design. Others include the the TMS320C6x VelociTI from Texas Instruments (Dallas, TX), the MAP1000 from Equator Technologies (Campbell, CA), and the TriMedia TM-1300 from Philips (Eindhoven, The Netherlands). As yet, only a few have been incorporated onto imaging boards by third-party developers (see "Image-processing boards use novel DSP designs to speed performance," p. 40).
Rather than call its design a VLIW implementation, Intel engineers have coined the term Explicitly Parallel Instruction Computing (EPIC) for the Merced, the company`s yet-to-be announced 64-bit microprocessor. "EPIC bears a striking resemblance to the Texas Instruments TMS320C6x VelociTI architecture," says Alexei Pylkin of the supercomputer software department RAS (Novosibirsk, Russia). "The TMS320C6201 DSP contains 32 general-purpose registers and uses a compiler to pack instruction words containing eight instructions along with a template that indicates dependencies between instructions," he says.
At Elbrus (Moscow, Russia), a processor is being developed that, according to chief technology officer Boris Babaian, will be two times faster than Merced`s successor, McKinley, when running at 1.2 GHz. Performance benchmarks for the yet-to-be-built E2K processor are targeted at 135 SPECint95 and 350 SPECfp95. According to A Guide to High-Performance Microprocessors (www.microprocessor.sscc.ru/news), the E2K project is a commercial version of the design already used in the Russian missile-defense system.