SoC verification system is fast

New generation of the PROC_SoC Verification System is designed to debug and verify SoC designs of diverse styles. Incorporating an Altera Stratix III EP3SL340 FPGA, the PROC_SoC has a flexible interconnect topology that allows any FPGA device to directly connect to any other programmable device in the system. It is designed to operate at clock speeds up to 300 MHz. Two scalable, multiple-board, card-cage-based configurations are available. The PROC_SoC system includes a comprehensive suite of software tools for implementing and debugging designs.
GiDEL
Or-Akiva, Israel
www.gidel.com