Auspy and GiDEL announce cooperative development relationship

FEBRUARY 4, 2008--Auspy Development (Cupertino, CA, USA; www.auspy.com), an independent supplier of partitioning tools for SoC prototyping, and GiDEL (Or-Akiva Israel; www.gidel.com), a supplier of reconfigurable systems for SoC verification and complex algorithm acceleration, have established a technology collaboration. Auspy and GiDEL will work closely to deliver full support of Auspy's ACE partitioning tool suite for the full range PROC systems used in the verification and debug of SoC designs. Auspy's ACE partitioner provides fully automatic and semi-automatic modes of operation and takes into consideration full timing characteristics of the single-board and multiple-board architectures within the PROC family of systems from GiDEL.

Of particular value is the support for hierarchy within the partitioning tool for the unique architecture of the PROC_SoC systems. The PROC_SoC can have up to ten dual FPGA boards, with more than 700 users defined any FPGA to any FPGA connections in 118 pin blocks. The partitioning tool will allow users to interactively guide the FPGA interconnection, or develop an interconnection map for the system's bus and cable types of high speed interconnections. The software will also enable users to take advantage of the LVDS support in the Stratix devices.

The PROC_SoC and PROC board-level reconfigurable systems feature advanced Altera Stratix II and Stratix III FPGAs that can be configured to emulate and verify complex SoC designs across a broad spectrum of applications over 100 million ASIC gates in complexity.