Packet switching serves next-generation interconnects

At the Embedded Systems Conference (Chicago, IL; Feb. 2000), Motorola (Austin, TX) and Mercury Computer Systems (Chelmsford, MA) announced the development of a switched-fabric interconnect architecture called RapidIO. Designed to enable chip-to-chip and board-to-board communications, RapidIO is a packet-switched interconnect technology that can provide performance levels scaling to 10 Gbit/s.

Motorola, Cisco Systems (San Jose, CA), Lucent Technologies (Murray Hill, NJ), and Nortel Networks (Brampton, Ontario, Canada) have established the RapidIO Trade Association (www.RapidIO.org) to direct the development of the technology. Other companies that plan to join this association include Galileo Technology (San Jose, CA), HAL Computer Systems (Campbell, CA), Seagull Semiconductor (Herzelia Pituah, Israel), Tundra Semiconductor (Kanata, Ontario, Canada), and Xilinx (San Jose, CA).

RapidIO interconnect technology can be used for PCI-to-PCI bridging with fewer pins and greater transmission distances. An InfiniBand host channel adapter can be provided if the system is designed into a wider system area network.

"Based on customer feedback, RapidIO addresses the interconnect challenges of next-generation networking systems," says Richard O'Connor, vice president of marketing at Tundra Semiconductor. "Traditional multidrop buses are reaching their connectivity and performance limits. Evolutionary, point-to-point system interconnects such as RapidIO will drive the architectures of future systems," he claims.

RapidIO is a communications standard for interconnecting circuit boards, as well as ICs on a circuit board, using a backplane. Unlike other bus technologies, which are targeted at the desktop PC and server computer markets, Motorola claims that RapidIO is designed for passing data and control information among microprocessors, DSPs, and memory and peripheral devices within a system (see figure on p. 13).

To replace common and proprietary processor and peripheral bus technologies, RapidIO defines physical-layer technology suitable for chip-to-chip and board-to-board communications across PCBs at throughputs exceeding 10 Gbit/s. This interconnect technology can also be bridged to other bus technologies, such as PCI and PCI-X, and to system area networks such as InfiniBand.

RapidIO uses the low-voltage differential signal standard, which is targeted toward short-distance board-level applications. Implemented in CMOS, its target frequencies of operation range from 250 MHz to more than 1 GHz.

Initially, 8- and 16-bit parallel point-to-point interfaces will be offered. These parts will contain an 8- or 16-bit input port and an 8- or 16-bit output port, both with clock and frame signals. Because data are sampled on both edges of the clock, resulting data rates in each direction can be scaled to 2 Gbyte/s for the 8-bit interface and 4 Gbyte/s for the 16-bit interface.

Mercury Computer is promoting a packet-switched interface that opposes the present circuit-switched implementations in its RACEway and RACE++ technologies. "Until we needed to go to clock rates greater than 200 MHz there was no need to move to the more complex implementation of packet switching," says Richard Jaenieke, director of product marketing at Mercury Computer. "Meanwhile, the technology for implementing packet-switching technology has improved to where we can implement it in a small silicon area."