Researchers accelerate tomographic image reconstruction with FPGA programming

JUNE 22, 2009--Impulse Accelerated Technologies (Kirkland, WA, USA; www.impulseaccelerated.com) announced the successful completion of a tomographic image reconstruction acceleration and benchmarking project at the University of Washington. Graduate researchers Nikhil Subramanian and Jimmy Xu, working under the direction of Scott Hauck, achieved 38 ms back-projection of a 512 x 512-pixel image from 512 projections. This represented a greater than 100X speedup over a software-only benchmark algorithm.

This project, which was funded in part by a $100,000 Research and Technology Development grant from Washington Technology Center (Seattle, WA, USA; www.watechcenter.org ), was intended to determine the benefits and tradeoffs of using higher-level FPGA programming methods for medical imaging, radar and other applications requiring high throughput image reconstruction.

Tomographic reconstruction is the process of creating cross-sectional images from data acquired by a scanner. Apart from medical imaging applications in X-ray, CT, and PET, these image processing techniques apply to a variety of other domains ranging from synthetic aperture radar (SAR) to electron microscopy.

In tomographic systems, the primary computational demand after data capture by the scanner is the back-projection of the acquired data into image space to reconstruct the internal structure of the scanned object. Back-projection can be viewed as a mapping of raw data space into a visible 2D or 3D image space. This process is highly demanding of computing resources.

The key to accelerating back-projection is to exploit parallelism in the computation. This is normally done by using processor clusters, but can also be accomplished using FPGA-based reconfigurable computing platforms. Working in cooperation with Adam Alessio of the University of Washington's Department of Radiology, the two researchers converted and refactored an existing back-projection algorithm, using both Impulse C and Verilog HDL, to evaluate design efficiency and overall performance.

This conversion, which included refactoring the algorithm for parallel execution in both C and Verilog, took 2/3 of the time when working in C than when working in Verilog. Perhaps more importantly, the two researchers found that later design revisions and iterations were much faster when working in C, with as little as 1/7 the time being required to make algorithm modifications when compared to Verilog. The team also reported that algorithm experiments performed quickly in Impulse C were useful when making subsequent improvements to the Verilog HDL version.

"The University of Washington team demonstrated just how productive C-to-FPGA methods can be," said David Pellerin, Impulse CTO. "The quick success of this project shows how even first-time users of Impulse C can rival the results achieved from hand-coding in HDL, with surprisingly little performance penalty and faster time-to-deployment."

Impulse and the University of Washington are making the source code for the back-projection algorithm available on request to other research teams involved with high performance reconfigurable computing. Impulse is actively seeking additional collaborations with FPGA research groups worldwide.

Impulse C has a growing community of universities and corporate researchers creating redeployable intellectual property for FPGAs. Much of this IP is available royalty free as part of Impulse C, or from the Impulse C user community. The University of Washington and Impulse are making the tomographic algorithm available upon request with no royalty charge. Interested parties should contact Impulse.

For more information, see the MS thesis of Nikhil Subramanian.

-- Posted by Conard Holton, Vision Systems Design, www.vision-systems.com